Introduction: Together with the ERIKA Enterprise OS commercialized by Evidence srl RTNS is one component of a rapid prototyping suite permitting to simulate and test real hardware distributed applications. ERIKA Enterprise is running on the popular Atmega 128 CPU platform, the microcontroller used in the Mica-2 and Mica-Z sensor boards commercialized by Crossbow Technology Inc.
	Experimental devices: In our experimental tests we used the Atmel STK-500/501 development board equipped with Atmega 128 CPU platform and AT86RF230 2.4 GHz transceiver peripheral as shown in the Figure on the left. We program the micro-controller through a JTag ICE mkII debugger making use of the facilities offered by the AVR-STUDIO IDE. To implement the Network Stack substrate we adapted the libraries provided by Atmel and compliant with the IEEE 802.15.4 standard. The Atmel set of functions, organized as a network library, have been linked to ERIKA core. In ERIKA, we used conditional compilation to customize the cases of ordinary devices and PAN coordinator. Specifically we provided the body for the callback functions involved in message receive and provide an API to handle the send.

Simple Experimental Setup: As a simple testbed we simulated a single clustered, star shaped, Wireless Sensor Network where four nodes located at the edges of a square generate Constant Bit Rate (15 Hz rate) traffic towards the Personal Area Network Coordinator, sitting in the center of mass of the figure. The latter is connected to a PC through a serial line. On the PC a server is running the Data AcQuisition (DAQ). In the initiating devices, two tasks are managed by ERIKA in FP: the net task taking care of the operations related to the Network Stack and the send task (with maximum priority) assuring a coherent trigger of periodic transmissions. In the recipient device, we modeled the activity of the WPAN coordinator with two tasks managed either using FCFS or FP: the net task and the load task modeling the computational activity. In the Atmega 128 microcontroller, the hardware interrupts raisen by the AT86RF230 transciever are mapped to the entry 11 of the interrupt vector. The Interrupt Service Routine (ISR) installed at that address in memory is the one of the Physical layer of the network library. The micro-controller executes such code at the arrival of a data frame.

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